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256K x 36, 512K x 18 3.3V Synchronous ZBTTM SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs Features
256K x 36, 512K x 18 memory configurations Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (5%) 3.3V (5%) I/O Supply (VDDQ) Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).
IDT71V65703 IDT71V65903
x x x x x x x x x x x x
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be it read or write. The IDT71V65703/5903 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903 tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen CEN is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip is deselected or a write is initiated. The IDT71V65703/5903 have an on-chip burst counter. In the burst mode, the IDT71V65703/5903 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V65703/5903 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18 CE1, CE2, CE2 OE R/W CEN BW1, BW2, BW3, BW4 CLK ADV/LD LBO ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, VDDQ VSS Address Inputs Chip Enables Output Enable Read/Write Signal Clock Enable Individual Byte Write Selects Clock Advance Burst Address/Load New Address Linear/Interleaved Burst Order Sleep Mode Data Input/Output Core Power, I/O Power Ground Input Input Input Input Input Input Input Input Input Input I/O Supply Supply Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Static Asynchronous Synchronous Static Static
5298 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
DECEMBER 2002
DSC-5298/03
1
(c)2002 Integrated Device Technology, Inc.
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol A0-A18 ADV/LD Pin Function Address Inputs Advance / Load I/O I I Active N/A N/A Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the inte rnal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the curre nt cycle takes place one clock cycle later. Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs re main unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V65703/5903 (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data b us will tri-state one clock cycle after deselect is initiated. Synchrono us active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted po larity but otherwise identical to CE1 and CE2. This is the clock input to the IDT71V65703/5903. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation. Asynchronous output enable. OE must be low to read data from the 71V65703/5903. When OE is HIGH the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. 3.3V core power supply. 3.3V I/O supply. Ground.
5298 tbl 02
R/W
Read / Write
I
N/A
CEN
Clock Enable
I
LOW
BW1-BW4
Individual Byte Write Enables
I
LOW
CE1, CE2
Chip Enables
I
LOW
CE2 CLK I/O0-I/O31 I/OP1-I/OP4 LBO
Chip Enable Clock Data Input/Output Linear Burst Order Output Enable
I I I/O I
HIGH N/A N/A LOW
OE
I
LOW
ZZ VDD VDDQ VSS
NOTE:
Sleep Mode Power Supply Power Supply Ground
I N/A N/A N/A
HIGH N/A N/A N/A
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42 2
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram 256K x 36
LBO Address A [0:17] CE1, CE2 CE2 R/W CEN ADV/LD BWx
Input Register
DI DO D Q Control D Q
256K x 36 BIT MEMORY ARRAY
Address
D Clk
Q
Control Logic
Mux
Clock
Sel
OE
Gate
Data I/O [0:31], I/O P[1:4]
5298 drw 01
,
6.42 3
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram 512K x 18
LBO Address A [0:18] CE1, CE2 CE2 R/W CEN ADV/LD BWx
Input Register
DI DO D Q Control D Q
512K x 18 BIT MEMORY ARRAY
Address
D Clk
Q
Control Logic
Mux
Clock
Sel
OE
Gate
Data I/O [0:15], I/O P[1:2]
5298 drw 01a
,
Recommended DC Operating Conditions
Symbol VDD VDDQ VSS VIH VIH VIL Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. 3.135 3.135 0 2.0 2.0 -0.3
(1)
Typ. 3.3 3.3 0
____ ____ ____
Max. 3.465 3.465 0 VDD + 0.3 VDDQ + 0.3 0.8
Unit V V V V V V
5298 tbl 04
NOTE: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2, once per cycle.
6.42 4
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature(1) 0C to +70C -40C to +85C VSS 0V 0V VDD 3.3V5% 3.3V5% VDDQ 3.3V5% 3.3V5%
5298 tbl 05
NOTES: 1. TA is the "instant on" case temperature.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VSS(1) VDD VDD(2) VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4
CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(3) A17 A8 A9
Pin Configuration 256K x 36
A6 A7 CE1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VSS(1) VDD ZZ I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1
5298 drw 02
,
NOTES: 1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is VIL. 2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH. 3. Pins 84 is reserved for a future 16M. 4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. The current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
LBO A5 A4 A3 A2 A1 A0 DNU(4) DNU(4) VSS VDD DNU(4) DNU(4) A10 A11 A12 A13 A14 A15 A16
Top View 100 TQFP
6.42 5
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 18
CE2 NC NC BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(3) A18 A8 A9 A6 A7 CE1
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Commercial TA(7) Industrial TBIAS TSTG PT IOUT Temperature Under Bias Storage Temperature Power Dissipation DC Output Current -40 to +85 -55 to +125 -55 to +125 2.0 50
o
Commercial & Industrial -0.5 to +4.6 -0.5 to VDD -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 0 to +70
Unit V V V V
o
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC NC VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VSS(1) VDD VDD(2) VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS VSS(1) VDD ZZ I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC
5298 drw 02a
VTERM(3,6) VTERM(4,6) VTERM(5,6)
C C C C
o o
W mA
5298 tbl 06
, NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. TA is the "instant on" case temperature.
NOTES: 1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH. 3. Pin 84 is reserved for a future 16M. 4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
100 TQFP Capacitance(1)
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 5 7 Unit pF pF
5298 tbl 07
LBO A5 A4 A3 A2 A1 A0 DNU(4) DNU(4) VSS VDD DNU(4) DNU(4) A11 A12 A13 A14 A15 A16 A17
Top View 100 TQFP
119 BGA Capacitance(1)
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 7 Unit pF pF
5298 tbl 07a
165 fBGA Capacitance(1)
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. TBD TBD Unit pF pF
5298 tbl 07b
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
6.42 6
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1 A B C D E F G H J K L M N P R T U VDDQ NC NC I/O16 I/O17 VDDQ I/O20 I/O22 VDDQ I/O24 I/O25 VDDQ I/O29 I/O31 NC NC VDDQ 2 A6 CE 2 A7 I/OP3 I/O18 I/O19 I/O21 I/O23 VDD I/O26 I/O27 I/O28 I/O30 I/OP4 A5 NC DNU(4) 3 A4 A3 A2 VSS VSS VSS BW3 VSS VDD(2) VSS BW4 VSS VSS VSS LBO A10 DNU(4) 4 NC(3) ADV/LD VDD NC CE1 OE A17 R/W VDD CLK NC CEN A1 A0 VDD A11 DNU(4) 5 A8 A9 A12 VSS VSS VSS BW2 VSS VSS(1) VSS BW1 VSS VSS VSS VSS(1) A14 DNU(4) 6 A16 CE2 A15 I/OP2 I/O13 I/O12 I/O11 I/O9 VDD I/O6 I/O4 I/O3 I/O2 I/OP1 A13 NC DNU(4) 7 VDDQ NC NC I/O15 I/O14 VDDQ I/O10 I/O8 VDDQ I/O7 I/O5 VDDQ I/O1 I/O0 NC ZZ VDDQ
5298 drw 13a
,
Top View Pin Configuration 512K x 18, 119 BGA
1 A B C D E F G H J K L M N P R T U VDDQ NC NC I/O8 NC VDDQ NC I/O11 VDDQ NC I/O13 VDDQ I/O15 NC NC NC VDDQ 2 A6 CE2 A7 NC I/O9 NC I/O10 NC VDD I/O12 NC I/O14 NC I/OP2 A5 A10 DNU(4) 3 A4 A3 A2 VSS VSS VSS BW2 VSS VDD(2) VSS VSS VSS VSS VSS LBO A15 DNU(4) 4 NC(3) ADV/LD VDD NC CE1 OE A18 R/W VDD CLK NC CEN A1 A0 VDD NC DNU(4) 5 A8 A9 A13 VSS VSS VSS VSS VSS VSS(1) VSS BW1 VSS VSS VSS VSS(1) A14 DNU(4) 6 A16 CE2 A17 I/O7 NC I/O5 NC I/O3 VDD NC I/O1 NC I/O0 NC A12 A11 DNU(4)
7 VDDQ NC NC NC I/O6 VDDQ I/O4 NC VDDQ I/O2 NC VDDQ NC I/OP1 NC ZZ VDDQ
5298 drw 13b
,
Top View
NOTES: 1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL. 2. J3 does not have to be connected directly to VDD as long as the input voltage is VIH. 3. A4 is reserved for future 16M. 4. DNU = Do not use; Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42 7
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 165 fBGA
1 A B C D E F G H J K L M N P R NC
(3)
2 A7 A6 NC I/O16 I/O18 I/O20 I/O22 VDD(2) I/O24 I/O26 I/O28 I/O30 NC NC(3) NC
(3)
3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4
4 BW3 BW4 VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A2 A3
5 BW2 BW1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DNU
(4)
6 CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
7 CEN R/W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
(1)
8 ADV/LD OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A10 A11
9 A17 NC(3) VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A13 A12
10 A8 A9 NC I/O15 I/O13 I/O11 I/O9 NC I/O7 I/O5 I/O3 I/O1 NC A14 A15
11 NC NC(3) I/OP2 I/O14 I/O12 I/O10 I/O8 ZZ I/O6 I/O4 I/O2 I/O0 I/OP1 NC A16
5298 tbl 25a
NC I/OP3 I/O17 I/O19 I/O21 I/O23 VSS (1) I/O25 I/O27 I/O29 I/O31 I/OP4 NC LBO
DNU(4) DNU
(4)
DNU(4) DNU
(4)
Pin Configuration 512K x 18, 165 fBGA
1 A B C D E F G H J K L M N P R NC(3) NC NC NC NC NC NC VSS (1) I/O12 I/O13 I/O14 I/O15 I/OP2 NC LBO 2 A7 A6 NC I/O8 I/O9 I/O10 I/O11 VDD(2) NC NC NC NC NC NC(3) NC
(3)
3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4
4 BW2 NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A2 A3
5 NC BW1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DNU
(4)
6 CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
7 CEN R/W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
(1)
8 ADV/LD OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A11 A12
9 A18 NC(3) VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A14 A13
10 A8 A9 NC NC NC NC NC NC I/O3 I/O2 I/O1 I/O0 NC A15 A16
11 A10 NC(3) I/OP1 I/O7 I/O6 I/O5 I/O4 ZZ NC NC NC NC NC NC A17
DNU(4) DNU
(4)
DNU(4) DNU
(4)
5298 tbl25b NOTES: 1. Pins H1 and N7 do not have to be connected directly to VSS as long as the input voltage is < VIL. 2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is > VIH. 3. Pin B9, B11, A1, R2 and P2 are reserved for a future 18M, 36M, 72M, 144M and 288M respectively. 4. DNU = Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42 8
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
CEN L L L L L L H R/W L H X X X X X CE1,CE2(5) L L X X H X X ADV/LD L L H H L H X BWx Valid X Valid X X X X ADDRESS USED External External Internal Internal X X X PREVIOUS CYCLE X X LOAD WRITE / BURST WRITE LOAD READ / BURST READ X DESELECT / NOOP X CURRENT CYCLE LOAD WRITE LOAD READ BURST WRITE (Advance burst counter)(2) BURST READ (Advance burst counter)(2) DESELECT or STOP(3) NOOP SUSPEND
(4)
I/O (One cycle later) D(7) Q(7) D(7) Q(7) HIZ HIZ Previous Value
5298 tbl 08
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state one cycle after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false. 6. Device Outputs are ensured to be in High-Z during device power-up. 7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
OPERATION READ WRITE ALL BYTES WRITE BYTE 1 (I/O[0:7], I/OP1)
(2) (2) (2,3) (2,3)
R/W H L L L L L L
BW1 X L L H H H H
BW2 X L H L H H H
BW3(3) X L H H L H H
BW4(3) X L H H H L H
5298 tbl 09
WRITE BYTE 2 (I/O[8:15], I/OP2)
WRITE BYTE 3 (I/O[16:23], I/OP3) WRITE BYTE 4 (I/O[24:31], I/OP4) NO WRITE
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Multiple bytes may be selected during the same cycle. 3. N/A for x18 configuration.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1 A1 First Address Second Address Third Address Fourth Address (1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 0 1 1 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 1 0 0 A0 1 0 1 0
5298 tbl 10
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.42 9
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Sequence 1 A1 First Address Second Address Third Address Fourth Address
(1)
Sequence 2 A1 0 1 1 0 A0 1 0 1 0
Sequence 3 A1 1 1 0 0 A0 0 1 0 1
Sequence 4 A1 1 0 0 1 A0 1 0 1 0
5298 tbl 11
A0 0 1 0 1
0 0 1 1
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE CLOCK ADDRESS (A0 - A17) CONTROL
(2) (2)
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
(R/W, ADV/LD, BWx) DATA
(2)
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
I/O [0:31], I/O P[1:4]
NOTES: 1. This assumes CEN, CE1, CE2 and CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock.
5298 drw 03
,
6.42 10
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+15 n+16 n+17 n+18 n+19 Address A0 X A1 X X A2 X X A3 X A4 X X A5 A6 A7 X A8 X A9 R/W H X H X X H X X L X L X X L H L X H X L ADV/LD L H L L H L H L L H L L H L L L H L H L CE1(1) L X L H X L X H L X L H X L L L X L X L CEN L L L L L L L L L L L L L L L L L L L L BWx X X X X X X X X L L L X X L X L L X X L OE X L L L X X L L X X X X X X X L X X L L I/O D1 Q0 Q0+1 Q1 Z Z Q2 Q2+1 Z D3 D3+1 D4 Z Z D5 Q6 D7 D7+1 Q8 Q8+1 Comments Load read Burst read Load read Deselect or STOP NOOP Load read Burst read Deselect or STOP Load write Burst write Load write Deselect or STOP NOOP Load write Load read Load write Burst write Load read Burst read Load write
5298 tbl 12
NOTES: 1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 2. H = High; L = Low; X = Don't Care; Z = High Impedence.
6.42 11
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation(1)
Cycle n n+1 Address A0 X R/W H X ADV/LD L X CE1(2) L X CEN L X BWx X X OE X L I/O X Q0 Comments Address and Control meet setup Contents of Address A0 Read Out
5298 tbl 13
NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation(1)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Address A0 X X X X A1 X A2 R/W H X X X X H X H ADV/LD L H H H H L H L CE1(2) L X X X X L X L CEN L L L L L L L L BWx X X X X X X X X OE X L L L L L L L I/O X Q0 Q0+1 Q0+2 Q0+3 Q0 Q1 Q1+1 Comments Address and Control meet setup Address A0 Read Out, Inc. Count Address A0+1 Read Out, Inc. Count Address A0+2 Read Out, Inc. Count Address A0+3 Read Out, Load A1 Address A0 Read Out, Inc. Count Address A1 Read Out, Inc. Count Address A1+1 Read Out, Load A2
5298 tbl 14
NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation(1)
Cycle n n+1 Address A0 X R/W L X ADV/LD L X CE1(2) L X CEN L L BWx L X OE X X I/O X D0 Comments Address and Control meet setup Write to Address A0
5298 tbl 15
NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Address A0 X X X X A1 X A2 R/W L X X X X L X L ADV/LD L H H H H L H L CE1(2) L X X X X L X L CEN L L L L L L L L BWx L L L L L L L L OE X X X X X X X X I/O X D0 D0+1 D0+2 D0+3 D0 D1 D1+1 Comments Address and Control meet setup Address A0 Write, Inc. Count Address A0+1 Write, Inc. Count Address A0+2 Write, Inc. Count Address A0+3 Write, Load A1 Address A0 Write, Inc. Count Address A1 Write, Inc. Count Address A1+1 Write, Load A2
5298 tbl 16
NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42 12
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Address A0 X A1 X X A2 A3 A4 R/W H X H X X H H H ADV/LD L X L X X L L L CE1(2) L X L X X L L L CEN L H L H H L L L BWx X X X X X X X X OE X X L L L L L L I/O X X Q0 Q0 Q0 Q1 Q2 Q3 Comments AddressA0 and Control meet setup Clock n+1 Ignored Address A0 Read out, Load A1 Clock Ignored. Data Q0 is on the bus. Clock Ignored. Data Q0 is on the bus. Address A1 Read out, Load A2 Address A2 Read out, Load A3 Address A3 Read out, Load A4
5298 tbl 17
NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation with Clock Enable Used(1)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Address A0 X A1 X X A2 A3 A4 R/W L X L X X L L L ADV/LD L X L X X L L L CE1(2) L X L X X L L L CEN L H L H H L L L BWx L X L X X L L L OE X X X X X X X X I/O X X D0 X X D1 D2 D3 Comments Address A0 and Control meet setup. Clock n+1 Ignored. Write data D0, Load A1. Clock Ignored. Clock Ignored. Write Data D1, Load A2 Write Data D2, Load A3 Write Data D3, Load A4
5298 tbl 18
NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42 13
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 Address X X A0 X A1 X X A2 X X R/W X X H X H X X H X X ADV/LD L L L L L L L L L L CE1(2) H H L H L H H L H H CEN L L L L L L L L L L BWx X X X X X X X X X X OE X X X L X L X X L X I/O(3) ? Z Z Q0 Z Q1 Z Z Q2 Z Comments Deselected. Deselected. Address A0 and Control meet setup. Address A0 read out, Deselected. Address A1 and Control meet setup. Address A1 read out, Deselected. Deselected. Address A2 and Control meet setup. Address A2 read out, Deselected. Deselected.
5298 tbl 19
NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used(1)
Cycle n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 Address X X A0 X A1 X X A2 X X R/W X X L X L X X L X X ADV/LD L L L L L L L L L L CE (2) H H L H L H H L H H CEN L L L L L L L L L L BWx X X L X L X X L X X OE X X X X X X X X X X I/O ? Z Z D0 Z D1 Z Z D2 Z Comments Deselected. Deselected. Address A0 and Control meet setup Data D0 Write In, Deselected. Address A1 and Control meet setup Data D1 Write In, Deselected. Deselected. Address A2 and Control meet setup Data D2 Write In, Deselected. Deselected.
5298 tbl 20
NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42 14
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V5%)
Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage Current LBO Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VDD = Max., VIN = 0V to VDD VDD = Max., VIN = 0V to VDD VOUT = 0V to VCC IOL = +8mA, VDD = Min. IOH = -8mA, VDD = Min. Min.
___
Max. 5 30 5 0.4
___
Unit A A A V V
___
___ ___
2.4
5298 tbl 21 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 3.3V5%)
7.5ns Symbol IDD Parameter Operating Power Supply Current CMOS Standby Power Supply Current Clock Running Power Supply Current Idle Power Supply Current Full Sleep Mode Supply Current Test Conditions Com'l Device Selected, Outputs Open, ADV/LD = X, VDD = Max., VIN > VIH or < VIL, f = fMAX(2) Device Deselected, Outputs Open, VDD = Max., VIN > VHD or < VLD, f = 0(2,3) Device Deselected, Outputs Open, VDD = Max., VIN > VHD or < VLD, f = fMAX(2,3) Device Selected, Outputs Open, CEN > VIH, VDD = Max., VIN > VHD or < VLD, f = fMAX(2,3) Device Selected, Outputs Open, CEN < VIL, VDD = Max., ZZ > VHD VIN > VHD or < VLD, f = fMAX(2,3) 275 Ind 295 Com'l 250 Ind 60 Com'l 225 Ind 60 mA 8ns 8.5ns Unit
ISB1
40
60
40
60
40
60
mA
ISB2
105
125
100
120
95
115
mA
ISB3
40
60
40
60
40
60
mA
IZZ
40
60
40
60
40
60
mA
5298 tbl 22
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Load
I/O
6 5 4 tCD 3 (Typical, ns) 2 1
VDDQ/2 50 Z0 = 50
5298 drw 04
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times 0 to 3V 2ns 1.5V 1.5V Figure 1
5298 tbl 23
,
Input Timing Reference Levels Output Reference Levels Output Load
Figure 1. AC Test Load
* **
20 30 50
*
*
200
5298 drw 05
80 100 Capacitance (pF)
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42 15
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V5%, Commercial and Industrial Temperature Ranges)
7.5ns Symbol Parameter Min. Max. Min. 8ns Max. Min. 8.5ns Max. Unit
tCYC tCH
(1)
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width
10 2.5 2.5
____
10.5 2.7 2.7
____
11 3.0 3.0
____
ns ns ns
____
____
____
tCL(1)
____
____
____
Output Parameters tCD tCDC tCLZ
(2,3,4)
Clock High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time Output Enable Low to Data Active Output Enable High to Data High-Z
____
7.5
____
____
8
____
____
8.5
____
ns ns ns ns ns ns ns
2 3
____
2 3
____
2 3
____
____
____
____
tCHZ(2,3,4) tOE tOLZ(2,3) tOHZ(2,3)
5 5
____
5 5
____
5 5
____
____
____
____
0
____
0
____
0
____
5
5
5
Set Up Times tSE tSA tSD tSW tSADV tSC tSB Hold Times tHE tHA tHD tHW tHADV tHC tHB Clock Enable Hold Time Address Hold Time Data In Hold Time Read/Write (R/W) Hold Time Advance/Load (ADV/LD) Hold Time Chip Enable/Select Hold Time Byte Write Enable (BWx) Hold Time 0.5 0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____ ____
Clock Enable Setup Time Address Setup Time Data In Setup Time Read/Write (R/W) Setup Time Advance/Load (ADV/LD) Setup Time Chip Enable/Select Setup Time Byte Write Enable (BWx) Setup Time
2.0 2.0 2.0 2.0 2.0 2.0 2.0
____ ____ ____ ____ ____ ____ ____
2.0 2.0 2.0 2.0 2.0 2.0 2.0
____ ____ ____ ____ ____ ____ ____
2.0 2.0 2.0 2.0 2.0 2.0 2.0
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns
0.5 0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____ ____
0.5 0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns
5298 tbl 24
NOTES: 1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ. 2. Transition is measured 200mV from steady-state. 3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.42 16
tCYC
CLK tSE tHE tCH tCL
CEN
tSADV tHADV
ADV/LD tSW tHW
R/W tSA tHA A2 tSC tHC
ADDRESS
A1
Timing Waveform of Read Cycle(1,2,3,4)
CE1, CE2(2)
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
6.42 17
tCD Q(A2) Q(A2+1) tCDC tCD Q(A2+2) Burst Read Read Q(A2+3)
BW1 - BW4
OE
(CEN high, eliminates current L-H clock edge) (Burst Wraps around to initial state)
tCLZ
tCHZ Q(A2+3) tCDC
5298 drw 06
DATAOUT
Q(A1)
Q(A2)
Read
,
NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM.
tCYC
CLK tSE tHE tCH tCL
CEN tHADV
tSADV
ADV/LD tSW tHW
R/W tSA tHA A2 tSC tHC
ADDRESS
A1
CE1, CE2(2) tSB tHB B(A2) B(A2+1) B(A2+2) B(A2+3) B(A2)
Timing Waveform of Write Cycles(1,2,3,4,5)
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
6.42 18
tSD tSD D(A2) D(A2+1) tHD D(A2+2)
Burst Write
BW1 - BW4
B(A1)
OE tHD
(CEN high, eliminates current L-H clock edge) (Burst Wraps around to initial state)
DATAIN
D(A1)
D(A2+3)
D(A2)
Write Write
5298 drw 07
NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
,
tCYC
CLK tSE tHE tCH tCL
CEN tHADV
tSADV
ADV/LD tSW tHW
R/W tSA tHA A2 A3 A6 A4 A5 A7 tSC tHC tSB tHB B(A2) B(A4) B(A5) B(A8) A8 A9
ADDRESS
A1
CE1, CE2(2)
Timing Waveform of Combined Read and Write Cycles(1,2,3)
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
6.42 19
tSD tHD D(A2) Write tCHZ tCLZ tCDC Q(A3) Q(A1) Read Write D(A4) Write D(A5)
BW1 - BW4
OE
DATAIN
D(A8) Write
tCD
DATAOUT
Q(A6) Read
Q(A7) Read
Read
5298 drw 08
,
NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
tCYC
CLK tSE tHE tCH tCL
CEN tSADV tHADV
ADV/LD tSW tHW
R/W tSA tHA A2 A3 tSC tHC tSB tHB B(A2) A4 A5
ADDRESS
A1
CE1, CE2(2)
Timing Waveform of CEN Operation(1,2,3,4)
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
6.42 20
tSD tHD tCHZ tCDC Q(A1) Q(A1) D(A2) tCD
BW1 - BW4
OE
DATAIN
tCD
tCDC Q(A3) Q(A4)
5298 drw 09
DATAOUT
tCLZ
,
NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
tCYC
CLK tSE tHE tCH tCL
CEN tSADV tHADV
ADV/LD tSW tHW
R/W tSA A1 tSC tHC tHA A2 A3 A4 A5
ADDRESS
CE1, CE2(2) tSB tHB B(A3)
Timing Waveform of CS Operation(1,2,3,4)
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
6.42 21
tSD tHD tCHZ tCD tCDC Q(A1) Q(A2) tCLZ D(A3)
BW1 - BW4
OE
DATAIN
DATAOUT
Q(A4)
Q(A5)
5298 drw 10
NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
,,
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42 22
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42 23
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
165 Ball Grid Array (fBGA) Package Diagram Outline
6.42 24
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE tOE tOHZ tOLZ Q
5298 drw 11
DATAOUT
Q
,
NOTE: 1. A read operation is assumed to be in progress.
Ordering Information
IDT XXXX Device Type S Power XX Speed XX Package X Process/ Temperature Range Blank I PF BG BQ 75 80 85 Commercial (0C to +70C) Industrial (-40C to +85C) 100-pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA)
,
Access time (tCD) in tenths of nanoseconds
IDT71V65703 IDT71V65903
256Kx36 Flow-Through ZBT SRAM 512Kx18 Flow-Through ZBT SRAM
5298 drw 12
6.42 25
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99 04/20/00 Pg.5,6 Pg. 7 Pg. 21 05/23/00 07/28/00 Pg. 23 Pg. 5-8 Pg. 7,8 Pg. 23 Pg. 8 Pg. 15 Pg. 1-25 Pg. 5,6,15,16,25 Pg. 1,2,5,6,7,8 Pg. 7 Created new part number and datasheet from 71V657/59 to 71v65703/5903 Add JTAG reset pins to TQFP pin configuration; removed footnote Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Add note to BGA pin configuration; corrected typo within pinout InsertTQFP Package Diagram Outline Add new package offering: 13mm x 15mm, 165 fine pitch ball grid array Correction on 119 Ball Grid Array Package diagram Outline Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and IDT71V658xx device errata sheet Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout Update BG119 package diagram dimensions Add reference note to pin N5 on the BQ165 pinout, reserved for JTAG TRST Add Izz to DC Electrical Characteristics Changed datasheet fromPreliminary to final release. Added I temp to datasheet Removed JTAG functionality for current die revision. Corrected pin configuration on the x36, 119 BGA. Switched pins I/O0and I/OP1.
11/04/00 12/04/02 12/18/02
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